1. Field of the Invention
The present invention relates to a data processing circuit and a solid-state imaging device.
Priority is claimed on Japanese Patent Application No. 2012-209541, filed Sep. 24, 2012, the content of which is incorporated herein by reference.
2. Description of Related Art
In recent years, a CMOS (Complementary Metal Oxide Semiconductor) image sensor has attracted attention and has been put to practical use as a solid-state imaging device. A CCD (Charge Coupled Device) image sensor is manufactured through a dedicated manufacturing process whereas a CMOS image sensor can be manufactured using a general semiconductor manufacturing process. Based on this, in the CMOS image sensor, for example, many functions can be realized by incorporating various functional circuits in the sensor like an SOC (System On Chip).
Also, in recent years, examples in which a solid-state imaging device including an analog-to-digital converter (hereinafter referred to as an “A/D conversion circuit”) is used as a solid-state imaging device having a digital camera, a digital video camera or an endoscope mounted thereon are increasing. In such an A/D conversion circuit included in the solid-state imaging device, a ramp type A/D conversion circuit may be used. When the A/D conversion circuit is described in the following description, the A/D conversion circuit is assumed to indicate a ramp type A/D) conversion circuit.
A solid-state imaging device includes a plurality of A/D conversion circuits having the same configuration, each including a comparator, an upper counter, a data processing circuit, and a memory. In each A/D) conversion circuit, the comparator performs a comparison (hereinafter referred to as a “comparison process”) of a voltage value of a pixel signal (an analog signal) with a voltage value of a reference signal in a ramp shape (ramp wave). Also, each A/D conversion circuit generates a digital signal corresponding to a size of each input pixel signal by the upper counter and the data processing circuit digitizing (binarizing) a time from a timing of an initial value of the ramp wave to a timing at which the comparison process is completed, as an upper-bit signal and a lower-bit signal of the digital signal, respectively, and the memory holding the digitized digital signal (see Japanese Patent Laid-Open Publication No. 2011-166235 and Japanese Patent Laid-Open Publication No. 2010-258806).
FIG. 20 is a block diagram illustrating a schematic configuration of a data processing circuit included in a conventional A/D conversion circuit. The conventional data processing circuit 900 illustrated in FIG. 20 includes a latch portion 901 and a digital generation unit 902.
The data processing circuit 900 generates and outputs the binarized digital signal by the latch portion 901 holding states of phases of a plurality of clock signals having different phases at certain intervals (hereinafter referred to as a “multi-phase clock”) at a timing at which the comparator has completed the comparison process, and the digital generation unit 902 digitizing the held states of the phases of the multi-phase clock. In the following description, numbers shown in brackets (“[ ]”) subsequent to a reference sign indicates the bit of each signal. For example, a signal of a second bit is indicated as “[1]” and a signal of a sixteenth bit is indicated as “[15].”
The latch portion 901 is a circuit that latches (holds) the state of the clock signal of each phase of the multi-phase clock DU, and includes the same number of latch circuits 91 as the number of multi-phase clocks DU.
A case in which the latch portion 901 included in the data processing circuit 900 illustrated in FIG. 20 includes sixteen latch circuits 91 (LAT[15:0]) corresponding to the respective phases of the multi-phase clock DU[15:0] of sixteen phases is shown.
In the latch portion 901 illustrated in FIG. 20, “LAT” is given as a reference sign of the latch circuit 91 and a number indicating each phase of the multi-phase clock DU is shown in brackets (“[ ]”) subsequent to the reference sign “LAT” in order to indicate the latch circuit 91 corresponding to each phase corresponding to a bit in the multi-phase clock DU, thereby indicating a bit of the latch circuit 91. For example, a fifteenth phase of the multi-phase clock DU is indicated by a multi-phase clock DU[14], and the latch circuit 91 corresponding to the multi-phase clock DU[14] is indicated by a latch circuit LAT[14].
Each latch circuit 91 latches (holds) a state of “high” or “low” of the clock signal of each phase of the corresponding multi-phase clock DU at a timing of a falling edge (or a rising edge) of the latch clock LATCLK indicating that the voltage value of the pixel signal (analog signal) and the voltage value of the reference signal in a ramp shape (ramp wave) match in the comparison process of the comparator, namely, indicating that the comparator has completed the comparison process.
Also, the latch portion 901 sequentially outputs an output signal DO[15:0] indicating states of clock signals of respective phases of the multi-phase clock DU latched in the latch circuits 91 to the readout line OL[1:0] according to a timing of readout switch signals SW1[14:0] and SW2[15:1] corresponding to the respective latch circuits 91.
The digital generation unit 902 is a circuit that binarizes the states of the phases of the multi-phase clock DU when the comparator has completed the comparison process based on the output signal DO[15:0] sequentially output from the latch portion 901 to the readout line OL[1:0] to generate a 4-bit digital signal DOUT[3:0], and includes, for example, an encoder 92 and a lower counter 93, as illustrated in FIG. 20.
The encoder 92 includes a general logic circuit, and generates a count clock CNTCLK to be counted by the lower counter 93, according to a signal of any 2 bits of the output signal DO[15:0] input by the readout line OL[1:0]. The lower counter 93 generates a binarized 4-bit digital signal DOUT[3:0] by counting the number of instances of “high” of the count clock CNTCLK.
FIG. 21 is a timing chart illustrating an example of a timing of the multi-phase clock and the latch clock input to the data processing circuit included in the conventional A/D conversion circuit. In FIG. 21, an example of the multi-phase clock DU[15:0] of sixteen phases having a phase difference of Ts/16 when a period of the clock signal of each phase of the multi-phase clock DU is a period Ts is illustrated.
As illustrated in FIG. 21, when the respective latch circuits 91 of the latch portion 901 latch the states of the clock signals of the respective phases of the corresponding multi-phase clock DU at a timing at which the latch clock LATCLK is inverted, the output signal DO[15:0] indicating the states of the clock signals of the respective phases of the multi-phase clock DU is “0000011111111000.” The data processing circuit 900 generates a 4-bit digital signal DOUT[3:0]=“1011” (“11” in decimal notation) by the digital generation unit 902 binarizing the states of the phases of the multi-phase clock DU based on the output signal DO[15:0].
Here, an operation when the digital generation unit 902 binarizes the states of the phases of the multi-phase clock DU will be described. FIG. 22 is a timing chart illustrating an example of a timing of an operation of binarizing states of phases of the multi-phase clock in the data processing circuit included in the conventional A/D conversion circuit.
The output signal DO[15:0] is sequentially output to the readout line OL[1:0] by 2 bits based on the readout switch signals SW1[14:0] and SW2[15:1], as illustrated in FIG. 22. In this case, the encoder 92 detects the state of the phase of the multi-phase clock DU, more specifically, a position of the bit of the latch circuit 91 in which there is a timing of a rising edge of the multi-phase clock DU, based on the readout line OL[1:0].
Also, the encoder 92 initiates generation of the count clock CNTCLK when the timing of the rising edge of the multi-phase clock DU is detected. When the output signal DO[15:0] of each latch circuit 91 of the latch portion 901 is “0000011111111000,” the encoder 92 generates a count clock CNTCLK which becomes “high” eleven times until reading of all bits of the output signal DO[15:0] ends, as illustrated in FIG. 22.
The data processing circuit 900 outputs a digital signal DOUT[3:0]=“1011” (“11” in decimal notation) obtained by binarizing the states of the phases of the multi-phase clock DU, as a lower-bit signal in the digital signals subjected to analog-to-digital conversion in the A/D conversion circuit, by the lower counter 93 counting the number of instances of “high” of the count clock CNTCLK.